1. Field of the Invention
The present invention relates to a semiconductor device and fabrication method thereof.
2. Description of the Related Art
For electric power converting apparatuses used in electric vehicles (EV), etc., the most widely used insulated gate semiconductor devices have lower power consumption and are easily driven in a voltage-controlled manner. Insulated gate semiconductor devices are known as an insulated gate field effect transistor (metal oxide semiconductor field effect transistor (MOSFET)), an insulated gate bipolar transistor (IGBT), etc.
In the present description and the accompanying drawings, “n” and “p” prefixes of layers and regions indicate that the majority of carriers is an electron and a hole, respectively. “+” and “−” appended to an “n” or a “p” indicate that the impurity concentration is higher and lower, respectively, than layers and regions without “+” and “−”.
FIG. 17 is a cross-sectional view of a conventional semiconductor device. For example, MOSFET of a trench gate structure will be described as a conventional insulated gate semiconductor device. A p-type base region 102 is disposed on a surface of a semiconductor substrate forming an n−-type drift region 101. A trench 103 is disposed penetrating the base region 102 and reaching the drift region 101. A gate electrode 105 is disposed inside the trench 103 via a gate insulating film 104. An n+-type source region 106 is selectively disposed on a surface layer of the base region 102 so as to be in contact with the trench 103. A source electrode 108 contacts the base region 102 and the source region 106. The source electrode 108 is electrically insulated from the gate electrode 105 by an interlayer insulating film 107. A drain electrode 109 is disposed on the backside of the semiconductor substrate.
Such a semiconductor device operates as follows. The source electrode 108 is in a state of being connected to the ground or of having a negative voltage applied thereto. The drain electrode 109 is in a state of having a positive voltage applied thereto. If a voltage lower than a threshold value is applied to the gate electrode 105, no current flows between the source and the drain since a p-n junction, made up of the base region 102 and the drift region 101, is inversely-biased. Therefore, the semiconductor device remains in the off-state. On the other hand, if a voltage exceeding the threshold value is applied to the gate electrode 105, in the p-type base region 102, a region in contact with the trench 103 beneath the source region 106 is inverted to become an n-type channel region. This causes an electron leaving the source electrode 108 to travel to the drain electrode 109 through an n-type region consisting of the channel region and the drift region 101 and current flows between the source and the drain, whereby the semiconductor device is turned on.
As such a semiconductor device, an apparatus is proposed that is configured as an insulated gate field effect transistor having a semiconductor substrate of a first conductivity type forming a drain region; a channel region of a second conductivity formed on a principal surface of the semiconductor substrate; a source region formed in the channel region; a gate insulating film and a gate electrode disposed across the source region and the drain region; and a source electrode in contact with a window surrounded by the gate electrode, where in the channel region of the window surrounded by the gate electrode, a recess portion is formed deeper than a channel region surface immediately under the gate insulating film, having a width reaching at least immediately under an end of the gate electrode. A back gate region is introduced into a bottom side region of the recess portion, and a source region of a silicide layer or a metal layer is disposed in the recess portion such that only the channel region and the back gate region are in contact with an inner surface of the source region (see, e.g., Japanese Laid-open Patent Publication No. 3197054).
A method of fabricating the conventional insulated gate semiconductor device depicted in FIG. 17 will be described. The p-type base region 102 is first formed on the surface of the semiconductor substrate forming the n−-type drift region 101. The trench 103 is then formed that penetrates the base region 102 and reaches the drift region 101. The gate electrode 105 is formed inside the trench 103 via the gate insulating film 104. The n+-type source region 106 is selectively formed on the surface layer of the base region 102 so as to be in contact with the trench 103. The interlayer insulating film 107, formed of a film such as phosphosilicate glass (PSG), is selectively formed on the surface of the semiconductor substrate to cover a surface of the gate electrode 105. The source electrode 108 is formed that contacts the base region 102 and the source region 106 exposed on the surface of the semiconductor substrate. The drain electrode 109 in contact with the drift region 101 is formed on the backside of the semiconductor substrate. This completes the MOSFET of the trench gate structure depicted in FIG. 17.
However, in conventional insulated gate semiconductor devices such as MOSFET and IGBT, a parasitic element such as a parasitic bipolar transistor and a parasitic thyristor are incidentally formed in addition to original constituent elements of the semiconductor devices. Such a parasitic element is likely to operate at abnormal times such as when an overcurrent flows in the semiconductor devices. It is problematic that the operation of the parasitic element adversely affects the operation of the original semiconductor devices.
For example, in the semiconductor device depicted in FIG. 17, a parasitic bipolar transistor 121 is formed that is made up of the drift region 101, the base region 102, and the source region 106. If an abnormal current such as overcurrent flows in the semiconductor device and a voltage drop in a channel region exceeds a forward voltage of a silicon diode, which is 0.7 V (because a built-in voltage of the diode is 0.6 V), the parasitic bipolar transistor 121 operates causing latch-up and short circuit. The operation of the parasitic bipolar transistor 121 cannot be controlled by controlling the voltage applied to the gate electrode 105. Therefore, destruction may occur if the semiconductor device exceeds a safe operation range.
A semiconductor device that avoids such a problem is known where size reduction is achieved by forming the source region 106 to have a narrower width, for example. However, the current density in a semiconductor device fabricated in this way is increased by the size reduction and the parasitic bipolar transistor 121 becomes more likely to operate. Another approach is known where the base region 102 of a semiconductor device is formed having a higher impurity concentration. However, a semiconductor device fabricated in this way becomes unable to sufficiently invert the channel region in the on-state. Therefore, the on-voltage problematically increases. Such a problem also occurs in IGBT of the trench gate structure.
To solve the problems of the conventional technologies described above, an object of the present invention is to provide a semiconductor device and fabrication method thereof capable of controlling the influence of a parasitic element. Another object of the present invention is to provide a semiconductor device and fabrication method thereof capable of preventing the on-voltage from increasing.